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Soutenance de thèse de Yazan BARAZI

by David Bonnafous - published on

Yazan BARAZI soutiendra ses travaux de thèse intitulés:

Fast short-circuit protection for SiC MOSFETs in extreme short-
circuit conditions by integrated functions in CMOS-ASIC technology

La soutenance se déroulera jeudi 1 octobre 2020 à 14h en salle des thèses (C002) à l’ENSEEIHT, 2 rue Charles Camichel 31000.

Meeting ID: 727 3973 6489
Passcode: 5RsvWq

Jury :
M. Nicolas ROUGER - CNRS, Institut National Polytechnique de Toulouse – LAPLACE – Directeur de thèse
M. Frédéric RICHARDEAU - CNRS, Institut National Polytechnique de Toulouse – LAPLACE – Co-directeur de thèse
M. Jean Christophe CREBIER - CNRS, Université Grenoble Alpes - G2Elab – Rapporteur
M. Nicolas GINOT - IUT de Nantes Département GE&II - IETR – Rapporteur
M. Stéphane AZZOPARDI} - Safran Tech – Examinateur
Mme Mounira BERKANI - UPEC-ESPE de Créteil - SATIE – Examinatrice
M. Marc COUSINEAU - Institut National Polytechnique de Toulouse - LAPLACE – Examinateur
M. Hassan MAHER - Université de Sherbrooke – Examinateur
M. Thierry SICARD - NXP Semiconductors – Invité

Abstract :
Wide bandgap power transistors such as SiC MOSFETs and HEMTs GaN push
furthermore the classical compromises in power electronics. Briefly, significant gains have been demonstrated: better efficiency, coupled with an increase in power densities offered by the increase in switching frequency. HV SiC MOSFETs have specific features such as a low short-circuit SC withstand time capability compared to Si IGBTs and thinner gate oxide, and a high gate-to-source switching control voltage. The negative bias on the gate at the off-state creates additional stress which reduces the reliability of the SiC MOSFET. The high positive bias on the gate causes a large drain saturation current in the event of a SC. Thus, this technology gives rise to specific needs for ultra-fast monitoring and protection. For this reason, the work of this thesis focuses on two studies to overcome these constraints, with the objective
of reaching a good performance compromise between “CMS/ASIC-CMOS technological integration level-speed–robustness”. The first one, gathers a set of new solutions allowing a detection of the SC on the switching cycle, based on a conventional switch control architecture with two voltage levels. The second study is more exploratory and is based on a new gate-driver architecture, called multi-level, with low stress level for the SiC MOSFET while maintaining dynamic performances. The manuscript covers firstly the SiC MOSFET environment, (characterization and properties of SC behavior by simulation using PLECS and LTSpice software) and covers secondly a bibliographical study on the Gate drivers. And last, an in-depth study was carried out on SC type I & II (hard switch fault) (Fault under Load) and their respective detection circuits. A test bench, previously carried out in the laboratory, was used to complete and validate the analysis-simulation study and to prepare test stimuli for the design stage of new solutions. Inspired by the Gate charge method that appeared for Si IGBTs and evoked for SiC MOSFETs, this method has therefore been the subject of design, dimensioning and prototyping work, as a reference. This reference allows an HSF type detection in less than 200ns under 400V with 1.2kV components ranging from 80 to 120mOhm.

Regarding new rapid and integrated detection methods, the work of this thesis focuses particularly on the design of a CMOS ASIC circuit. For this, the design of an adapted gate driver is essential. An ASIC is designed in X-Fab XT-0.18 SOI-CMOS technology under Cadence, and then packaged and assembled on a PCB. The PCB is designed for test needs and adaptable to the main bench. The design of the gate driver considered many functions (SC detection, SSD, segmented buffer, an "AMC", ...). From the SC detection point of view, the new integrated monitoring functions concern the V GS time derivative method which is based on a detection by an RC analog shunt circuit on the plateau sequence with two approaches: the first approach is based on a dip detection, i.e. the presence or not of the Miller plateau. The second approach is based on slope detection, i.e. the variability of the input capacitance of the power transistor under SC-HSF compared to normal operation. These methods are compared in the third chapter of the thesis, and demonstrate fault detection times between 40ns and 80ns, and preliminary robustness studies and critical cases are presented. A second new method concerns the variability of the charge quantity of an auxiliary "sensor" capacitance at the drain potential, partially integrated into the ASIC. This sensor capacitance also plays the role of an isolator.

In addition to the main study, an exploratory study has focused on a modular architecture for close control at several bias voltage levels taking advantage of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and improve their reliability through active and dynamic multi-level selection of switching sequences and on/off states.

CMOS design - Analog and Digital Electronics - Power Electronics - Control of Wide Band Gap transistors - Gate Driver - MOSFET SiC - Short-Circuit & Protection